1. Field of the Invention
The present invention relates to a transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method having a so-called metastability measure.
2. Description of the Related Art
An apparatus such as, for example, a personal computer or a server often employs a configuration with a circuit responsible for general-purpose operations incorporated into a semiconductor chip and a circuit specific to each user incorporated into FPGA (field programmable gate array) such that the apparatus is operated by mutually sending and receiving signals between the semiconductor chip and the FPGA from a cost standpoint.
Such a configuration produces a problem of a signal transmission method between the semiconductor chip and the FPGA. Since the operation clock frequency of the semiconductor chip is typically different from the operation clock frequency of the FPGA, it is problematic that a receiving flip-flop oscillates (a so-called metastable phenomenon occurs) depending on signal acquisition timing on the reception side. That is, if a signal level is changed at the timing of signal acquisition by the receiving flip-flop, it is not determined whether the signal level is high or low, resulting in oscillation of the receiving flip-flop.
A circuit with a few flip-flops connected in series is conventionally used as a so-called metastability measure for preventing this oscillation phenomenon (see, e.g., Japanese Patent Kokai No. 2008-242527). FIG. 1 is a block diagram of a conventional metastability measure circuit 400. The metastability measure circuit 400 consists of a first flip-flop 410 and a second flip-flop 420 mutually connected in series. The first flip-flop 410 acquires in synchronization with a receiving clock RC a signal DI changing in level in synchronization with a sending clock to retain the signal. The second flip-flop 420 acquires the signal level retained by the first flip-flop 410 in synchronization with the receiving clock RC to retain and output the signal level as a signal DO having the signal level retained by the second flip-flop 420. In such a configuration, even when the first flip-flop 410 is in the oscillating state, the second flip-flop 420 stably acquires a signal level after the oscillation has converged. Therefore, the output of the signal DO is stabilized. Such a metastability measure using a few flop-flops is often used in a transmission apparatus for transmitting a control signal.
However, such a conventional metastability measure circuit has the following problems. A first problem is that a control signal pulse is unable to be received correctly on the reception side. The control signal is often sent and received as a pulse with one clock width. In this case, for example, if the frequency of the operation clock on the reception side is lower than the frequency of the operation clock on the transmission side, the control signal pulse cannot be acquired on the reception side, resulting in so-called control signal pulse loss. On the other hand, if the frequency of the operation clock on the transmission side is lower than the frequency of the operation clock on the reception side, one control signal pulse is acquired for a plurality of times on the reception side, leading to the operation same as the case of receiving a plurality of control signal pulses. Therefore, even the usage of the conventional metastability measure circuit cannot solve the problem generated because the operation clock frequencies are different between the transmission side and the reception side.
A second problem is a delay of the control signal. The frequency of the operation clock of FPGA is typically lower than the frequency of the operation clock of a semiconductor chip. If the conventional metastability measure circuit is used when FPGA is on the reception side, a delay of the control signal received by the FPGA increases within the circuit. If the conventional metastability measure circuit is used, a delay of two cycles of the operation clock is generated between reception and output of the control signal by the FPGA. If the frequency of the operation clock of the FPGA is lower, the delay of two cycles is a considerable delay.